Expert in Digital Test Engineering

Overview Senior Digital Test Engineer

Key Responsibilities Lead the design execution of silicon design for next-generation accelerator chips using high-performance computing and artificial intelligence.

Develop DFT architecture and implement effective DFM concepts to meet product specifications and production requirements.

Collaborate with cross-function teams to implement test solutions that meet requirements and ensure product quality.

Contribute to target coverage requirements for logic, memories, IO, and mixed-signal IPs.

Requirements 10+ years of experience in IC digital design with multiple cycles of DFT and RTL design.

Good knowledge of MBIST Insertion, Compression Insertion, Scan Stitching, OCC insertion, iJTAG.

Good understanding of ATPG, Pattern Generation, Simulation.

Hands on Experience in DFT Flow bring up using scripting languages like TCL / Perl / Makefile based.

Bonus points for knowledge of NOC architecture, RISC-V ISA / architecture, and SOC based on this processor.

Additional Information Relocation and visa support are available.

Must be prepared to work 3 days per week onsite in Barcelona.

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