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Design Verification Engineer
TechTeamZMadrid, Kingdom Of Spain, EspañaHace más de 30 días
Descripción del trabajoMaster's or PhD in EE / CS. 5–8+ years in digital verification (SystemVerilog / UVM). Strong scripting and simulation tool experience. Fluent English. Excellent problem-solving skills. RISC-V core or SoC verification experience. Knowledge of vector / tensor compute or memory architectures.
Overview
About this role
We are seeking an experienced Digital Verification Engineer to lead the development of our next-generation AI / ML compute platforms.
Main Responsibilities
- Develop and execute UVM-based testbenches for complex IP and SoCs.
- Apply formal and dynamic verification techniques.
- Drive coverage analysis, regressions, and debug.
- Closely collaborate with design and architecture teams.
- Automate verification workflows (Python, Bash, Tcl).
Requirements
Nice to Have
About Us
We are a fast-growing European semiconductor company developing high-performance RISC-V cores with vector / tensor acceleration and proprietary high-bandwidth memory IP.
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Design Engineer • Madrid, Kingdom Of Spain, España
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