Design Analysis Engineer

Digital ASIC Design Engineer – Madrid

A leader in advanced semiconductor innovation, is seeking a Digital ASIC Design Engineer to join their team working on high-performance ASICs, SoCs, and FPGAs across a variety of next-generation products. This is an opportunity to contribute to the full development lifecycle—from specification and architecture through to final validation—on designs that push the boundaries of performance, power efficiency and integration.

This role is ideal for an experienced Digital ASIC Design Engineer who thrives in technically diverse environments and enjoys seeing their designs come to life in real-world applications. You will be joining a collaborative team of experts where innovation and quality are equally prioritised.

Key Responsibilities :

Design and implement digital blocks for ASICs, SoCs, and FPGAs, from concept through to validation.

Participate in all key stages of the digital design flow, including synthesis, timing closure, and place & route.

Support backend teams in resolving timing and layout challenges.

Contribute to lab-based FPGA emulation and system-level validation.

Assist in bringing ASICs to market through silicon validation, characterisation, and qualification activities.

What We’re Looking For :

A Master’s degree (or equivalent) in Electrical, Electronics, or Computer Engineering.

Minimum of 4 years' experience in ASIC or FPGA design.

Practical knowledge of digital design languages such as Verilog and SystemVerilog.

Hands-on experience with industry-standard tools such as Synopsys DC, VCS, Questa, or Vivado.

Familiarity with system-level integration and protocols (e.G. wireless, video, networking, or logic-based design).

Exposure to verification methodologies like UVM or OVM is highly desirable.

Clear communicator, with the ability to work effectively in cross-functional teams.

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