Senior Verification Engineer - Uvm / Systemverilog / Python / Perl / Bash / Tcl

Verification Engineer - UVM / SystemVerilog / Python / Perl / Bash / TCL Are you a Mid to Senior level Senior Verification Engineer looking for you next challenge? Have experience with SystemVerilog and UVM, plus scripting in Python, Perl, Bash, or TCL? Want to join a very exciting Spain based semiconductor company? If you can say to this, then please keep reading. We're partnered with a genuinely exciting Barcelona HQ'd semiconductor organization and they're seeking a number of Mid-to-Senior Verification Engineers to join them on a permanent basis, working fully onsite in central Barcelona. This company has some very aggressive growth plans and need to hire at least 20 engineers over the next 18 months. Visa sponsorship is available if needed, not to mention free Spanish lessons to help you assimilate in Spain. Required skills : MSc or PhD in a related field 4 years relevant experience Proficiency in SystemVerilog and UVM Knowledge of scripting languages (Python, Perl, Bash, TCL) and regression tools Experience with simulation and simulation tools Knowledge of revision control methodology and tools (git, svn) Experience in block level and sub-system or top level verification Experience with formal and dynamic verification Strong problem-solving skills and attention to detail Excellent communication and teamwork abilities Sound good? In return you'll receive an excellent yearly salary, flexible work schedules, and very good career progression, whilst working within a team of extremely talented individuals. If this sounds interesting and you'd like to learn more, click the link below to apply or email me with a copy of your resume on By applying to this role you understand that we may collect your personal data and store and process it on our systems. For more information please see our Privacy Notice (