Senior RTL Engineer

Overview :

Join a dynamic team working on advanced RISC-V processor designs targeting cutting-edge technology nodes. Focus areas include processor pipelines, caches (L1 / L2), and custom memory controllers. We seek engineers who deeply understand the architecture and can translate complex problems into efficient RTL implementations.

Key Responsibilities

• Design and develop RTL for critical processor components (pipeline, d-cache, i-cache, L2 pipeline)
• Collaborate closely on microarchitecture and system-level design
• Deliver clean, maintainable Verilog code aligned with project requirements

Requirements