Physical Verification Engineer
We are seeking a highly skilled Physical Design Engineer with expertise in Physical Verification (PV) to join our cutting-edge semiconductor design team.
This position involves ensuring design signoff quality for advanced technology nodes, utilizing strong knowledge of industry-standard PV tools, flows, and methodologies. The ideal candidate will have hands-on experience solving PV issues and collaborating with other teams to resolve violations efficiently.
Responsibilities :
- Drive Physical Verification signoff including DRC, LVS, PERC, and Antenna checks at advanced process nodes.
- Collaborate with Place and Route, STA, and Layout teams to resolve PV violations efficiently.
- Develop, maintain, and optimize PV methodologies and runsets for low-nm nodes.
- Communicate with chip foundries to align on rule decks and signoff criteria.
- Support tape-out readiness by ensuring PV closure with clean signoff results.
Requirements :
Bachelor's or Master's in Electrical Engineering, Computer Engineering, or related field.3+ years of experience in Physical Design with a strong focus on Physical Verification.Hands-on expertise with PV tools such as Mentor Calibre, Synopsys ICV.Solid understanding of low-nanometer process design rules, reliability checks, and foundry requirements.Proven track record in advanced node tapeouts (7nm, 5nm, 3nm or below).Preferred Qualifications :
Experience with ECO flows and integration with Place & Route.Knowledge of DFM (Design for Manufacturability) and reliability verification (EM / IR, ESD).Exposure to Flip-Chip / Advanced Packaging physical verification.