Job Title : Senior Verification Engineer
We are seeking a skilled Senior Verification Engineer to join our team in Barcelona.
This is an exciting opportunity for someone who wants to make a meaningful contribution to the development of complex digital systems.
Main Responsibilities :
- Perform block-level, sub-system, and top-level RTL verification
- Develop and execute verification plans using SystemVerilog and UVM
- Create and maintain testbenches, test cases, and assertions
- Use formal and dynamic verification techniques
- Collaborate closely with cross-functional teams
- Maintain thorough documentation and help improve verification flows
Requirements :
6+ years of industrial experience in digital design verificationAdvanced degree (Master's or PhD) in Electrical / Computer Engineering or related fieldStrong proficiency in SystemVerilog, UVM, and simulation toolsExperience with scripting languages (Python, Perl, Bash, TCL) and regression toolsFamiliarity with version control systems (git, svn)Strong analytical and debugging skillsExcellent English communication skillsWhy Work with Us?
We offer a supportive environment, career growth opportunities, flexible working hours, competitive salary, and more. Come work with us in beautiful Barcelona!