Digital ASIC Design Expert

Overview As a key member of our team, you will contribute to the full development lifecycle of high-performance ASICs, SoCs, and FPGAs across various next-generation products.

Responsibilities You will design and implement digital blocks for ASICs, SoCs, and FPGAs from concept through to validation.

You will participate in all key stages of the digital design flow, including synthesis, timing closure, and place & route.

You will support backend teams in resolving timing and layout challenges.

You will contribute to lab-based FPGA emulation and system-level validation.

You will assist in bringing ASICs to market through silicon validation, characterisation, and qualification activities.

Qualifications A Master\'s degree (or equivalent) in Electrical, Electronics, or Computer Engineering.

Minimum of 4 years\' experience in ASIC or FPGA design.

Practical knowledge of digital design languages such as Verilog and SystemVerilog.

Hands-on experience with industry-standard tools such as Synopsys DC, VCS, Questa, or Vivado.

Familiarity with system-level integration and protocols (e.g. wireless, video, networking, or logic-based design).

Exposure to verification methodologies like UVM or OVM is highly desirable.

We are looking for a clear communicator who can work effectively in cross-functional teams. If you have the passion and expertise to drive innovation in digital ASIC design, we encourage you to apply.

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