Advanced Technology Node Engineer

Senior RTL Designer Role We are seeking an experienced engineer with expertise in RTL design or microarchitecture to contribute to a cutting-edge RISC-V project on an advanced technology node.

Responsibilities Implement and optimize RTL for RISC-V components.

Design and verify PCS and FEC algorithms.

Integrate and test Ethernet SERDES PHY and controller blocks.

Apply timing constraints and perform thorough timing analysis.

Collaborate with cross-functional teams to ensure design correctness.

Mentor and guide junior engineers where appropriate.

Qualifications Bachelor's degree in Computer Science, Electrical Engineering, or a related field.

Proficiency in English (C1 level).

Strong experience in Verilog and RTL design.

Knowledge of timing analysis and timing constraints.

Hands-on experience with PCS and FEC algorithm implementation.

Familiarity with Ethernet SERDES PHY and controller integration.

Scripting skills (Python, Perl, Bash, Tcl, or equivalent).

Leadership or mentoring experience.

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