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Physical Verification
SemidynamicsCatalonia, EspañaHace 16 días
Descripción del trabajoBachelor’s or Master’s in Electrical Engineering, Computer Engineering, or related field. 3+ years of experience in Physical Design with a strong focus on Physical Verification. Hands-on expertise with PV tools such as Mentor Calibre, Synopsys ICV. Solid understanding of low-nanometer process design rules, reliability checks, and foundry requirements. Proven track record in advanced node tapeouts (7nm, 5nm, 3nm or below). Strong scripting skills (TCL, Python, Shell) to drive automation. Experience with ECO flows and integration with Place & Route. Knowledge of DFM (Design for Manufacturability) and reliability verification (EM / IR, ESD). Exposure to Flip-Chip / Advanced Packaging physical verification.
We are looking for a highly motivated Physical Design Engineer with deep expertise in Physical Verification (PV) to join our cutting-edge semiconductor design team. You will play a critical role in ensuring design signoff quality for advanced technology nodes. This position requires strong knowledge of industry-standard PV tools, flows, and methodologies, as well as hands-on experience on solving PV issues.
Requirements
- Drive Physical Verification signoff including DRC, LVS, PERC, and Antenna checks at advanced process nodes.
- Collaborate with Place and Route, STA, and Layout teams to resolve PV violations efficiently.
- Develop, maintain, and optimize PV methodologies and runsets for low-nm nodes.
- Communicate with chip foundries to align on rule decks and signoff criteria.
- Support tape-out readiness by ensuring PV closure with clean signoff results.
- Automate flows and scripts to improve PV productivity, turnaround time, and reliability.
Required Qualifications
Preferred Qualifications
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Verification • Catalonia, España
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