Senior Digital Design Engineer

Overview

Join a world-class semiconductor design team in Barcelona, developing advanced cache and memory subsystem architectures for next-generation SoCs.

Responsibilities

• Architect and implement cache & memory subsystems for high-performance SoCs
• Design RTL using Verilog / VHDL, ensuring timing and power efficiency
• Work with cache coherency protocols (CHI, CXL) and define address maps
• Conduct timing analysis, constraints, and block-level testing
• Automate design / verification flows with Python, Perl, Bash, or TCL
• Collaborate with CPU, interconnect, and verification teams
• Manage revisions and workflows using Git / SVN

What you’ll bring

Why join

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