Multi-core Verification Engineer (RE1)

Barcelona Supercomputing CenterBarcelona, Cataluña, España

Hace 8 días

Descripción del trabajo

Multi-core Verification Engineer (RE1)

Position : Multi-core Verification Engineer (RE1) – Barcelona Supercomputing Center (BSC-CNS)

Reference : 644_25_CS_V_RE1

Closing Date : Tuesday, 11 November 2025

About BSC : The Barcelona Supercomputing Center is the leading supercomputing center in Spain. It hosts MareNostrum, one of Europe’s most powerful supercomputers, and is a founding member of PRACE and host for EuroHPC JU. The mission of BSC is to research, develop and manage information technologies to facilitate scientific progress.

Context & Mission : BSC is constructing a full RISC-V ecosystem, from processor design to tape‑out and software stack. This vacancy is for a junior verification engineer working on the verification of out‑of‑order RISC‑V cores and vector extensions in a multi‑core system.

Key Duties

Verify complex digital designs focused on RISC‑V cores, caches, and accelerators, and their integration in a multi‑core system.
Collaborate closely with design and verification engineers on active projects, performing hands‑on verification and contributing to design, build, and integration.
Build efficient verification environments using UVM, SystemVerilog, and problem‑solving skills, exercising processor designs through corner‑cases and exposing bugs.
Participate in the full verification life cycle : planning, test and assertion implementation, failure triaging, debugging, coverage definition, and related tasks.

Requirements

Education : BS or MS in Electrical Engineering, Computer Engineering, or equivalent.

Experience developing UVM environments, simulating tests, debugging failures, and documenting results.

Developing and debugging scalar and vector tests for single‑core and multi‑core versions.

Support for complex bare‑metal environments (virtual memory, context switching, trap handling).

Advanced knowledge of compilation and linking processes.

Experience with cache coherency and multi‑core memory models.

Knowledge of industry‑standard simulators (Model / QuestaSim, VCS, etc.) and revision control & regression systems.

Proficiency in UVM, SystemVerilog Assertions, functional coverage, and random verification techniques.

Strong debugging skills and ability to collaborate with design engineers.

Programming experience in Python, Perl, Bash, or Tcl for support adjustments and flow customization; familiarity with Linux.

Deep understanding of multi‑core architectures and modern processor microarchitecture.

Experience with RISC‑V ISAs and their implementation in in‑order and out‑of‑order cores.

Experience with vector architectures, especially the RISC‑V V‑extension.

Ability to work independently, take initiative, prioritize, and meet deadlines.

Excellent written and verbal communication skills.

Conditions

Location : BSC Computer Sciences Department.

Contract : Full‑time (37.5 h / week) with flexible working hours, training plan, insurance, relocation support.

Duration : Open‑ended contract.

Holidays : 23 paid vacation days plus selected holidays.

Salary : Competitive and commensurate with qualifications.

Start date : 01 December 2025.

Applications

Please send a full CV in English, a cover / motivation letter, and two references through the BSC website. Applications without these documents will not be considered.

BSC-CNS is committed to equal opportunities and welcomes applications from all qualified candidates regardless of race, color, religion, sex, gender identity, national origin, age, disability, or other protected status.

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Engineer • Barcelona, Cataluña, España