ROLE : Senior Digital Design Engineer – Memory Subsystems
LOCATION : Barcelona, Spain
SALARY : Negotiable
DURATION : Permanent
We are looking for a Senior Digital Design Engineer to design and develop high-performance memory subsystems for modern SoCs. You will work within the Memory Design Team and collaborate closely with other engineers to create efficient and robust memory architectures.
Responsibilities :
- Define, design, and implement memory controllers and subsystems (DDR, HBM)
- Develop and verify RTL (Verilog or VHDL) for memory blocks
- Work with timing constraints and perform block-level testing
- Integrate memory IPs into SoC environments
- Collaborate with cross-functional teams to ensure coherency and high-performance operation
Required :
8+ years of industrial experience in digital designStrong knowledge of DDR or HBM memoriesProven experience designing or integrating memory controllersHands-on experience with AXI protocolProficiency in RTL design (Verilog or VHDL)Experience with timing constraints and basic block-level testingDesired :
Master’s degree or PhDScripting skills (Python, Perl, Bash, TCL)Experience with version control (git, svn)Knowledge of coherency concepts and protocolsExperience defining memory maps