Id. Eures : Associate Engineer Functional Verification

Senior Verification Engineer - UVM / SystemVerilog / Python / Perl / Bash / TCL

We are partnered with a Barcelona-based semiconductor company seeking mid- to senior-level Verification Engineers to join on a permanent basis, working onsite in central Barcelona. Visa sponsorship is available, and Spanish lessons are provided.

• MSc or PhD in a related field
• 4+ years relevant experience
• Proficiency in SystemVerilog and UVM
• Knowledge of scripting languages (Python, Perl, Bash, TCL) and regression tools
• Experience with simulation and simulation tools
• Knowledge of revision control methodology and tools (git, svn)
• Experience in block level and sub-system or top level verification
• Experience with formal and dynamic verification
• Strong problem-solving skills and attention to detail
• Excellent communication and teamwork abilities

In return you'll receive an excellent yearly salary, flexible work schedules, and strong career progression within a team of highly talented individuals.

If this sounds interesting and you'd like to learn more, click the link below to apply or email a copy of your resume to

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