Senior Digital Design Engineer
BeagleCequelinos, Galicia, SPAINHace 2 días
Descripción del trabajo4+ years industrial experience (Engineer) or 6+ years (Lead) Strong hands-on experience with PCIe (design and / or integration) Solid background in SoC / ASIC IP integration Proficiency in RTL design (Verilog or VHDL) Experience with basic block-level testing Familiarity with at least one protocol : AXI, CHI, or AHB Master's degree or PhD Knowledge of C++, Python, Perl, Bash, or TCL Experience working with version control (git, svn) Understanding of coherency protocols Experience with CXL Exposure to common digital design tools (Synthesis, STA, CDC, Lint, etc.)
ROLE : PCIe Lead / Senior Digital Design Engineer
LOCATION : Barcelona, Spain
SALARY : Negotiable
DURATION : Permanent
We're looking for an experienced engineer to take a leading role in the design and integration of PCIe solutions within complex SoC / ASIC environments. If you're passionate about microprocessor architecture, high-speed I / O, and building high-performance subsystems, this role puts you at the centre of it.
What you'll be doing :
- Own the architecture and lead the RTL implementation of PCIe subsystems
- Drive efficient interaction between the PCIe block and CPU clusters using AMBA-CHI coherency
- Integrate and verify IPs within large SoC environments
- Work closely with cross-functional teams of digital, verification, and architecture experts
What you'll bring :
Nice to have :
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Design Engineer • Cequelinos, Galicia, SPAIN
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