▷ Busqueda Urgente Senior Rtl Designer

ROLE : Senior RTL DesignerLOCATION : Barcelona, SpainSALARY : NegotiableDURATION : PermanentDescriptionWe are looking for an engineer with deep expertise in RTL design or microarchitecture to contribute to a cutting-edge RISC-V project on an advanced technology node. The role focuses on PCS and FEC implementation and requires a hands-on approach where you take ownership of solving complex design challenges down to the RTL level. You will collaborate closely with the architecture and verification teams to deliver robust, high-performance designs.ResponsibilitiesImplement and optimize RTL for RISC-V componentsDesign and verify PCS and FEC algorithmsIntegrate and test Ethernet SERDES PHY and controller blocksApply timing constraints and perform thorough timing analysisCollaborate with cross-functional teams to ensure design correctnessMentor and guide junior engineers where appropriateRequirementsBachelor’s degree in Computer Science, Electrical Engineering, or a related fieldProficiency in English (C1 level)Strong experience in Verilog and RTL designKnowledge of timing analysis and timing constraintsHands-on experience with PCS and FEC algorithm implementationFamiliarity with Ethernet SERDES PHY and controller integrationScripting skills (Python, Perl, Bash, Tcl, or equivalent)Leadership or mentoring experience