Physical Verification

We are looking for a highly motivated Physical Design Engineer with deep expertise in Physical Verification (PV) to join our cutting-edge semiconductor design team. You will play a critical role in ensuring design signoff quality for advanced technology nodes. This position requires strong knowledge of industry-standard PV tools, flows, and methodologies, as well as hands-on experience on solving PV issues.

Requirements

• Drive Physical Verification signoff including DRC, LVS, PERC, and Antenna checks at advanced process nodes.
• Collaborate with Place and Route, STA, and Layout teams to resolve PV violations efficiently.
• Develop, maintain, and optimize PV methodologies and runsets for low-nm nodes.
• Communicate with chip foundries to align on rule decks and signoff criteria.
• Support tape-out readiness by ensuring PV closure with clean signoff results.
• Automate flows and scripts to improve PV productivity, turnaround time, and reliability.

Required Qualifications

Preferred Qualifications