ROLE : Senior RTL Designer LOCATION : Barcelona, Spain SALARY : Negotiable DURATION : Permanent Description We are looking for an engineer with deep expertise in RTL design or microarchitecture to contribute to a cutting-edge RISC-V project on an advanced technology node. The role focuses on PCS and FEC implementation and requires a hands-on approach where you take ownership of solving complex design challenges down to the RTL level. You will collaborate closely with the architecture and verification teams to deliver robust, high-performance designs. Responsibilities Implement and optimize RTL for RISC-V components Design and verify PCS and FEC algorithms Integrate and test Ethernet SERDES PHY and controller blocks Apply timing constraints and perform thorough timing analysis Collaborate with cross-functional teams to ensure design correctness Mentor and guide junior engineers where appropriate Requirements Bachelor’s degree in Computer Science, Electrical Engineering, or a related field Proficiency in English (C1 level) Strong experience in Verilog and RTL design Knowledge of timing analysis and timing constraints Hands-on experience with PCS and FEC algorithm implementation Familiarity with Ethernet SERDES PHY and controller integration Scripting skills (Python, Perl, Bash, Tcl, or equivalent) Leadership or mentoring experience
Senior Designer • Barcelona, Catalonia, España