Team Lead, Digital Design Verification

About Corinex

At Corinex, we are driving the future of energy with cutting-edge Smart Grid technology. As a global leader in smart grid solutions, we enable utilities to enhance grid visibility, flexibility, and decarbonization- supporting the seamless integration of renewable energy, electric vehicles, and heat pumps into the power grid. Headquartered in Vancouver, Canada, Corinex is the market leader in Europe, particularly in Spain, where our Smart Grid solutions are deployed by major DSOs (Distribution System Operators) to improve grid operations. With successful implementations across global markets, our technologies accelerate the transition to a more sustainable, decentralized, and efficient energy infrastructure. Recognized as a key contributor to industry standards and a 2024 Deloitte Technology Fast 50 winner, Corinex is shaping the future of smart energy.

To strengthen our team in Spain, we are seeking an experienced and motivated Digital Verification Team Lead.

About The Role

We are looking for a Digital Design Verification Team Lead to join our Valencia R&D team. The candidate will be integrated into a dynamic, cross-functional, experienced team to do functional verification tests in Verilog and C, for million-plus gate ASICs targeted for Smart Grid applications. Work directly with ASIC and board designers to ensure a smooth transition from project definition through prototyping to mass production. Define and implement test procedures to ensure the maximum level of product quality. Improve manufacturing yields and costs through creative thinking and innovative ideas. This is a Full-time, permanent, remote position working on cutting-edge semiconductor technologies, particularly in high-speed networking and embedded systems.

Responsibilities

• Build up and manage Digital Verification Team.
• Verify highly complex SoCs and support verification development.
• Architect and develop the functional verification environment, including reference models, testbench development, and testcase execution.
• Write test plans using random techniques and coverage analysis.
• Work closely with mixed signal teams for integration of high-speed analog behavioral models.
• Debug failures and work with designers to resolve issues.
• Cooperate with Synthesis, DFT, STA, PnR to implement subsystems that meet challenging PPA requirements.
• Support Emulation, functional ATE, and silicon validation teams.

Qualifications

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